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TFDU5107
Vishay Semiconductors
Integrated Low Profile Transceiver Module for Telecom Applications 9.6 kbit/s to 1.152 Mbit/s Data Transmission Rate
Description
The miniaturized TFDU5107 in the well-known Baby Face package is an ideal transceiver for applications in telecommunications like mobile phones, pagers, and PDAs of all kinds. The devices are designed for optimum performance and minimum package size. The device covers the IrDA(R) physical layer specification with SIR specification and 1.152 Mbit/s IrDA(R) mode. The new features A current limiter is implemented to operate the device whitout external resistor in an IrDA compliant mode (> 1 m). For reduced current as for the "Low Power" mode a current limiting resistor might be added. The device covers the supply voltage from 3.6 V down to 2.4 V and with its low power consumption it is optimum suited for battery powered applications. Double eye safety protection by pulse duration and current limitation is integrated. As additional feature the logic voltage swing Vlogic can be set externally.
Features
D Package: - TFDU5107 Universal (Baby Face) - SMD Side and Top View Solderability D Internal IRED current limition to operate without external resistor. With external resistor adaptable to power reduced operation as IrDA "Low Power" Standard D Wide Supply Voltage Range (2.4 V to 3.6 V) D Operational down to 2.0 V D Logic Input and Output Voltage 1.5 V to 5.5 V set by external control pin D Tri - State - Receiver Output D Lowest Power Consumption, typically 500 A in Receive Mode, <1 A Shutdown, only typical 5 mA Average Current Consumption in SIR and 1.152 Mbit/s Transmit Mode in Low Power IrDA mode D Fewest External Components D High EMI Immunity D Eye Safety Protection Integrated D Pin Assignment Backward Compatible to Legacy Baby Face Package
Applications
D Mobile Phones, Pagers, Hand-held Battery Operated Equipment D Computers (WinCE, PalmPC, PDAs) D Digital Still and Video Cameras D Extended IR Adapters D Medical and Industrial Data Collection
Package
TFDU5107 Baby Face (Universal)
Document Number 82534 Rev. A1.4, 01-Nov-02
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TFDU5107
Vishay Semiconductors Ordering Information
Part Number TFDU5107-TR3 TFDU5107-TT3 Qty / Reel 1000 pcs 1000 pcs Description Oriented in carrier tape for side view surface mounting Oriented in carrier tape for top view surface mounting
Functional Block Diagram
VCC Vlogic
Driver Amplifier Comparator Rxd IRED Anode SD Txd AGC Logic Current controlled driver IRED Cathode
GND Figure 1. Functional Block Diagram
Pin Description
Pin Number 1 Description I/O IRED Anode to be externally connected to directly to VCC. Alternatively the current can be decreased by an external resistor.This pin is allowed to be supplied from an uncontrolled power supply separated from the controlled VCC supply IRED Cathode IRED Cathode, internally connected to driver transistor Txd Transmit Data Input I Rxd Received Data Output, push-pull CMOS driver output capable O of driving a standard CMOS or TTL load. No external pull-up or pull-down resistor is required. Pin is floating with a weak pull up to VCC, when device is in shutdown mode. Rxd output is quiet during transmission. SD Shutdown, will switch the device into shutdown after a delay I of 1 ms VCC Supply Voltage Vlogic Defines the input and output logic swing voltage I GND Ground Baby Face (Universal) Function IRED Anode Active
2 3 4
HIGH LOW
5 6 7 8
HIGH
Figure 2. Pinning
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TFDU5107
Vishay Semiconductors Absolute Maximum Ratings
Reference Point Ground, Pin 8, unless otherwise noted Parameters Supply Voltage Range y g g Test Conditions 0 V < Vdd2 < 6 V 0 V < Vdd1 < 6 V 0 V < Vdd2 < 6 V 0 V < Vdd1 < 6 V All Pins (Pin 1 excluded) Pin 4 Pin 1, ton< 20%, < 20 s Symbol Vdd1 Vdd2 Vlogic Min. -0.5 -0.5 -0.5 Typ. Max. 6 6 6 10 25 500 125 450 125 85 85 240 6 Vlogic+0.5 2.8 *) (500) **) Unit V V V mA mA mA mA mW C C C C V V mm mW/sr
Input Current Output Sink Current, Rxd Rep. Pulsed IRED Current Average IRED Current Power Dissipation Junction Temperature Ambient Temperature Range (Operating) Storage Temperature Range Soldering Temperature Transmitter Data and Shutdown Input Voltage Receiver Data Output Voltage Virtual Source Size
IIRED(RP) IIRED(DC) Ptot TJ Tamb Tstg
-25 -25 215 -0.5 -0.5 2.5
t = 20 s @215C 2.4 V < Vdd1 < 5.5 V
VTxd, VSD VRxd d Ie
Method: (1-1/e) encircled energy Maximum Intensity for Class 1 IEC60825-1 or EN60825-1, edition Jan.2001 *) **)
Due to the internal limitation measures the device is a "class 1" device IrDA specifies the max. intensity with 500 mW/sr
Document Number 82534 Rev. A1.4, 01-Nov-02
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TFDU5107
Vishay Semiconductors Optoelectronic Characteristics
Tamb = 25C, Vdd1 = 2.4 V to 3.6 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameters Transceiver Supported Data Rates Rxd pulse duration 400 ns Base band SIR mode Base band 1.152 Mbit/s Supply Voltage Range Supply Voltage Supply Current receive mode Supply Current shutdown mode Average Supply Current *) Standart MIR transmit mode Ie > 100 mW/ sr specified operation Vdd2 = 2.4 V to 3.6 V Vdd1 = 2.4 V to 3.6 V Vdd1 = 2.4 V to 3.6 V Vdd1 = 2.4 V to 3.6 V, above Vdd1 =3.3 V a serial resistor for reducing the internal power dissipation should be implemented, e.g. RL = 2.7 Vdd2 = 2.4 V to 3.6 V Vdd1 Vdd2 IS ISSD IS 9.6 9.6 2.4 2.4 500 0.1 60 115.2 1152 3.6 3.6 900 1 110 kbit/s kbit/s V V A A mA Test Conditions Symbol Min. Typ. Max. Unit
Logic Voltage Range Shutdown / Mode clock pulse duration Shutdown delay "Receive off" Shutdown Delay "Receive on" Transceiver "Power On" Settling Time *)
Vlogic tprog tprog tprog
1.5 0.2 1 40
3.6 20 1.5 100 50
V s ms s s
Time from switching on Vdd1 to established specified operation
Maximum data is for 20% (25%) duty cycle for SIR (MIR 1.152 Mbit/s) Low power mode. The typical value is given for the case of normal operation with statistical and equal "0" and "1" - distribution.
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Document Number 82534 Rev. A1.4, 01-Nov-02
TFDU5107
Vishay Semiconductors Optoelectronic Characteristics
Tamb = 25C, Vdd1 = 2.4 V to 3.6 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameters Receiver Minimum Detection Threshold Irradiance SIR 9.6 kbit/s to 115.2 kbit/s *) Minimum Detection Threshold Irradiance 9.6 kbit/s to 1.152 Mbit/s *) Maximum Detection Threshold Irradiance || 15 Vdd1 = 2.4 V to 3.6 V || 15 Vdd1 = 2.4 V to 3.6 V || 90 Vdd1 = 5 V || 90 Vdd1 = 3 V Logic Low Receiver Input Irradiance Output Voltage Rxd Active C = 15 pF, R = 2.2 k Non active C = 15 pF, R = 2.2 k Output Current Rxd VOL < 0.8 V Rise Time @Load: C = 15 pF, R = 2.2 k Fall Time @Load: C = 15 pF, R = 2.2 k Rxd Signal Electrical Output Pulse Width Latency *) Rxd output pulse duration 400 ns 1.5 V Vlogic 5.5 V 1.5 V Vlogic 5.5 V 1.5 V Vlogic 5.5 V tr tf tp tL 20 20 300 400 100 Ee, min 20 35 mW/m 2 Test Conditions Symbol Min. Typ. Max. Unit
Ee, min
50
80
mW/m 2
Ee, max Ee, max Ee,max,low VOL VOH
3300 8000 4
5000 15000
W/m 2 W/m 2 mW/m 2
0.5 Vlogic-0.5
0.8
V V
4 70 70 500 200
mA ns ns ns s
Document Number 82534 Rev. A1.4, 01-Nov-02
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TFDU5107
Vishay Semiconductors Optoelectronic Characteristics
Tamb = 25C, Vdd1 = 2.4 V to 3.6 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameters Transmitter Logic CMOS High/Low Decision Threshold Logic Low Transmitter Input Voltage VIL(Txd) VIL(Txd) 0 0.8*) Vlogic 400 110 23 1.45 210 880 45 0.04 25 tj 0.2 250 320 80 1.75 226 40 900 1/2xVlogic 0.2*) Vlogic Vlogic +0.5 V V V mA mW/sr s s ns ns nm nm W/sr % s Test Conditions Symbol Min. Typ. Max. Unit
Logic High Transmitter Input Voltage 1.5 V < Vlogic < 3.6 V VIH(Txd) Current Limitation Output Radiant Intensity, || 15 Standard MIR level Maximum Output Pulse width (eye safety protection) Optical Pulse width Optical Rise/Falltime Peak Wavelength of Emission Spectral Optical Radiation Bandwidth Output Radiant Intensity Overshoot, Optical Rising Edge Peak to Peak Jitter Txd logic low level Vdd1 = 3.3 V IF6 = 400 mA resistor limited PWI > 23 s PWI = 1.6 s PWI = 217 ns IF Ie PWOmin PWO PWO tr, tf p
*)
Switch, current can be defined by external resistor, internal current limitation to 500 mA peak
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Document Number 82534 Rev. A1.4, 01-Nov-02
TFDU5107
Vishay Semiconductors Recommended SMD Pad Layout
The leads of the device should be soldered in the center position of the pads.
7x1=7 0.6 ( 0.7)
2.5 ( 2.0) 1
16524
8 1
Figure 3. TFDU5107 Baby Face (Universal)
Recommended Solder Profile
240 210 Temperature ( C )
2 - 4C/s
10 s max. @ 230C
Current Derating Diagram
600 Peak Operating Current ( mA ) 500 400 300 200 100 0 -40 -20 0
14875 Current derating as a function of the maximum forward current of IRED. Maximum duty cycle: 25%.
180 150 120 90 60 30 0 0 50 100
120 - 180 s 90 s max.
2 - 4C/s
14874
150 200 250 Time ( s )
300
350
20 40 60 80 100 120 140 Temperature ( C )
Figure 4. Recommended Solder Profile
Figure 5. Current Derating Diagram
Document Number 82534 Rev. A1.4, 01-Nov-02
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TFDU5107
Vishay Semiconductors
Identification
The identification of the device can be recalled by setting the SD active followed by activating Txd for a short period. With the low going edge of Txd a single pulse is generated at Rxd. The SD is intendet to activate the shutdown function after a delay of 1 ms. Therefore the full sequence should be run with that 1 ms time limitation, see drawing.
tSD: > 5 ms for "real" shutdown > 1 ms
SD
tTxd: > 0.5 ms to 2 ms
Txd
tdelTxd: 1 ms tdelRxd: 10 ns
tRxd = 400 ns
Rxd
Figure 6.
Vlogic Setting
The logic voltage swing is set by applying an external voltage to the Vlogic pin.
Table 1. Truth table
Inputs SD Txd Optical input Irradiance mW/ m2 x x x x <4 > 40 Rxd
Outputs LED drive current resulting intensity Ie in mW/ sr 0 0 10 < Ie < 300 defined by an external resistor 0 0 0
high < 1 ms high > 1 ms low low low low
pulse x high high > 80 s low low
low going Txd triggers monostable to edit a 400 ns low pulse floating (500 k to Vdd) high high high low, pulse of 400 ns edge triggered
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Document Number 82534 Rev. A1.4, 01-Nov-02
TFDU5107
Vishay Semiconductors TFDU5107 - Baby Face (Universal) Package (Mechanical Dimensions)
12249
Document Number 82534 Rev. A1.4, 01-Nov-02
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TFDU5107
Vishay Semiconductors Appendix
Application Hints
The TFDU5107 do not need any external components when operated at a "clean" power supply. In a more power supply noisy ambient it is recommended to add a combination of a resistor and capacitor (R1, C1, C2) for noise suppression as shown in the figure below. A combination of a electrolytic for the low frequency range and a ceramic capacitor for suppressing the high frequency disturbance will be most effective. The capacitor C3 is only necessary when inductive wiring is used or the power supply cannot deliver the operating peak pulse current. The inputs TXD and SD are high impedance CMOS inputs. Therefore, the lines from the I/O to those inputs should be carefully designed not to pick up ambient noise. If long lines are used, loads at the Txd input of the TFDx5x07 and at the Rxd input of the controller (!) are recommended. At the IRED Anode voltage supply line an additional capacitor might be necessary when inductive wiring is used. However, a low impedance layout is the better and more cost efficient solution. For adjusting the intensity depending on the application, see the diagrams.
500 5.25V 400 Intensity (mW/sr) 5.0V 300 200 100 0 0
15186
max. intensity in emission cone "15 min. Rdson, min. VF
5.0V max.Rdson, max.VF Vcc=4.75V min. intensity in emission cone "15 2 4 6 8 10 12 14 Current Control Resistor ( W ) 16
Figure 8. Intensity Ie vs. Current Control Resistor R2 5 V Applications
700 600
max. intensity in emission cone "15 min. Rdson, min. VF 3.6V 3.3V min. intensity in emission cone "15 max. Rdson, max. VF 3.3V Vcc=3.0V
Recommended Circuit Diagram
C1, (C3): 4.7 F, see text C2: 470 nF R1 VCC1 GND Rxd VCC2 Txd SD Vlog C3 R2 4 1 3 5 7 Rxd Vdd2, IRED Anode Txd SD Vlogic
15187
Intensity (mW/sr)
500 400 300 200 100 0 0
TFDU5107
6 8 Vdd1 GND
C2
C1
2
4 6 8 10 Current Control Resistor ( W )
12
Figure 9. Intensity Ie vs. Current Control Resistor R1, 3 V Applications
Latency
Figure 7. Recommended Application Circuit
Shut Down
To shut down the TFDx5x07 into a standby mode the SD pin has to be set active. After a delay of < 1 ms it will switch to the standby mode.
The receiver is in specified conditions after the defined latency. In a UART related application after that time (typically 50 s) the receiver buffer of the UART must be cleared. Therefore, the transceiver has to wait at least the specified latency after receiving the last bit before starting the transmission to be sure that the corresponding receiver is in a defined state.
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Document Number 82534 Rev. A1.4, 01-Nov-02
TFDU5107
Vishay Semiconductors
Table 1. Recommended Application Circuit Components
Component C1, C3 C2 R1 R2
Recommended Value 4.7 mF, 16 V 0.1 F, Ceramic
47 , 0.125 W 5 V supply voltage: 14 , 0.25 W (recommend using two 6.8 W, 0.125 W resistors in series) 3.0 V supply voltage: 4.5 , 0.25 W (recommend using two 2.3 W, 0.125 W resistors in series)
Vishay Part Number 293D 475X9 016B 2T VJ 1206 Y 104 J XXMT CRCW-1206-47R0-F-RT1 CRCW-1206-6R80-F-RT2
CRCW-1206-2R26-F-RT1
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TFDU5107
Vishay Semiconductors Revision History:
A1.1a, 19/12/1999:Slightly changed feature description. The pins 6 and 7 are exchanged by customer demand. A1.2, 12/07/2000: Rxd Rise time and Fall time reduced typos corrected A1.3, 13/10/2000: Typos corrected A1.4, 01/11/2002: Eye safety statement adapted to the latest standard version
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Document Number 82534 Rev. A1.4, 01-Nov-02
TFDU5107
Vishay Semiconductors Ozone Depleting Substances Policy Statement
It is the policy of Vishay Semiconductor GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs). The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. Vishay Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. Vishay Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances.
We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use Vishay Telefunken products for any unintended or unauthorized application, the buyer shall indemnify Vishay Telefunken against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. Vishay Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 (0)7131 67 2831, Fax number: 49 (0)7131 67 2423
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